Sparse data processing workloads such as graph analytics perform irregular memory accesses. In some cases, these accesses are to large data structures, and are pseudo-random. In modern processors, full cache lines are fetched from memory and inserted into a cache memory. However, in many cases these lines are evicted before any reuse (either from spatial or temporal locality). This leads to both cache pollution and waste of external memory bandwidth. Newer memory interfaces provide fine-grain memory access capabilities, namely memory access less than a given memory line or cache line width. However sub-cache line memory accesses lead to partial cache lines in a processor cache hierarchy, which can complicate cache design.